1. Field of the Invention
The present invention relates to a clock signal generation circuit, and more particularly to a clock signal generation circuit used as a clock generator which receives a reference clock signal and generates a prescribed clock in response to the reference clock signal, and is equipped with a detective circuit to detect the loss of the reference clock.
2. Description of the Related Art
The clock signal plays the basic role in the operational sequence in, for example, a microcomputer system. As a clock source for generating the clock signal, is used to be made of a clock signal with certain duty cycle given by a crystal oscillator.
Recently, accompanying the increase in the clock rate of the clock signal, the clock signal is being made of a phase locked loop (referred to as "PLL" hereinafter) frequency synthesizer circuit which enables to obtain a stabilized high frequency clock using a relatively low frequency reference clock as an input. The PLL circuit is typically composed of a phase (and/or frequency) comparator (referred to as "PFC" hereinafter), a filter, a voltage controlled oscillator (referred to as "VCO" hereinafter) and a frequency divider circuit.
In this oscillator, a output clock signal with multiplied frequency is obtained based on the frequency of a reference clock signal generated by a reference oscillator, such as a crystal oscillator. However, the problem of these oscillators is the loss of the clock signal that is used as the reference of these oscillators. The reference clock signal generated by the crystal oscillator can be lost due to mechanical or some other reasons, which significantly affects the reliability of the system using the reference clock signal. It is for this reason that a technique of detecting the loss of the reference clock is disclosed in Japanese Laid-Open Patent Application No. Hei 2-112008. The contents of the application will be described briefly as a prior art in what follows.
A block diagram of a conventional clock generator is shown in FIG. 8. This clock generator includes an oscillator circuit (referred to as "X-OSC" hereinafter) 11, a clock signal detect and limp mode control circuit (referred to as "limp control circuit" hereinafter) 81 to generate a stable clock signal without the loss of an external reference clock signal, a phase comparator 82, a filter 83, a voltage control circuit (referred to as "VCC" hereinafter) 84, a VCO 16 and a frequency divider 17.
A crystal 10 is coupled between an EXTAL pin and an XTAL pin connected to the X-OSC 11. The X-OSC 11 outputs a reference clock signal XTALCLK. The reference clock signal XTALKCLK is inputted respectively to the limp control circuit 81 and the phase comparator 82. The frequency divider 17 outputs a divided clock signal MCCLK as its output signal. The divided clock signal MCCLK is also inputted respectively to the limp control circuit 81 and the phase comparator 82. The phase comparator 82 generates a signal LOCK and a phase error signal in accordance with the reference clock signal XTALCLK and the divided clock signal MCCLK, and the signal LOCK and the phase error signal are inputted to the limp control circuit 81 and the filter 83, respectively. The limp control circuit 81 generates a filter enable signal FILTEN and a reference voltage enable signal REFEN. The filter 83 generates a control voltage signal as its output in accordance with the phase error signal and the signal FILEN. The control voltage signal and one of the outputs, the signal REFEN, of the limp control circuit 81 are inputted to the VCC 84, and its output signal VCOIN is input to the VCO 16 as a control voltage. The VCO 16 generates as its output a controlled clock signal VCOCLK in accordance with the signal VCOIN which is input to the frequency divider 17 that generates the divided clock signal MCCLK. Further, the VCO 16 gives various clock signals used in a clock control circuit in the system (not shown specifically).
The device shown in FIG. 8 performs the well-known operation as a PLL frequency synthesizer if the operations of the limp control circuit 81 and the voltage control circuit 84 were absent. The loop circuit comprising the phase comparator 82, the filter 83, the VCO 16 and the frequency divider 17 receives the reference clock signal XTALCLK as a frequency reference signal and generates a synthesized controlled clock signal VCOCLK. The frequency of the controlled clock signal VCOCLK is related to the frequency of the reference clock signal XTALCLK. Namely, if the frequency divider 17 outputs an n-demultiplied clock with respect to the input clock, then, in the phase locked state, the frequency F of the controlled clock signal VCOCLK is determined in terms of the frequency f of the reference clock signal XTALCLK according to the following equation. EQU F=n.times.f (1)
The design, manufacture and operation of the PLL frequency synthesizer are the technologies well known in the semiconductor industries, so that it will be unnecessary to give a further detailed description.
Now, if the reference clock signal XTALCLK is lost, the limp control circuit 81 detects the event and changes the signal REFEN from the inactive to the active level. As a result of the shift of the signal REFEN to the active level, the voltage control circuit 84 changes over the control voltage to be given to the VCO 16 from a voltage based on the output signal of the filter 83 to a voltage based on the signal REFEN of the VCC 84. This means that the loop condition no longer exists, and the output of the VCO 16 is a clock signal which does not depend on the reference clock signal XTALCLK, with its frequency determined by the reference voltage generated by the VCC 84. This frequency of the voltage control clock signal VCOCLK based on the signal REFEN is generally set, although not always the case, to give the voltage control clock signal VCOCLK with a frequency which is much lower than that given in the normal operation mode. The purpose of changing frequency of the voltage control clock signal VCOCLK is to provide an operation in which sequentially correct stoppage of the functions of the system (as data processing unit 1) or the continuation of operation of the system at a low level processing capacity can be attained, rather than to aim at maintaining of the system operation as well as the normal operation mode.
FIG. 9 shows a block diagram of the limp control circuit 81. The input to the limp control circuit 84 comprises the signals XTALCLK, MCCLK, RST and LOCK. The signal RST is a signal which is generated when the phase locked condition is destroyed corresponding to the starting up the system or an intentional external factor such as the change of the frequency division ratio, clock stoppage or the like by user or user program. The remaining signals have been described in the above.
The signal LOCK and the signal RST are inputted to the set input and the reset input terminals, respectively, of a flip-flop 91 (referred to as "FF" hereinafter) 91.
A shift register 92 which receives the reference clock signal XTALCLK to its IN input terminal, the divided clock signal MCCLK to its CLK input terminal, and the output of an inverted AND (referred to as "NAND" hereinafter) gate 94 which is obtained by NOT-ANDing the output of the FF 91 and the reference clock signal XTALCLK to its input terminal RES, and a shift register 93 which receives the output of a NAND gate 94 to its IN input terminal, the signal MCCLK to its input terminal CLK, and the output of a NAND gate 95 which is obtained by NOT-ANDing the output of the FF 91 and the output of the NAND gate 94 to its input terminal RES, input the overflow (referred to as OVF hereinafter) outputs from their respective shift registers to an OR gate 96, and the output of the OR gate 96 is inputted to a limp mode control signal generating circuit 97. The limp mode control signal generating circuit (referred as to "LMCSGC" hereinafter) 97 eventually generates and outputs control signals REFEN and FILTEN in response to the input from the OR gate 96.
The FF 91 plays the role of a register which indicates that the PLL is brought to the locked condition during the system starting up, the FF 91 is reset by bringing the RST signal goes to the active level when the locked condition of the PLL does not hold. The FF 91 is set by the LOCK signal goes to active in the locked state wherein the phase difference is found to fall within a prescribed error range by the phase comparator (shown in FIG. 8). In this way, the loss of the reference clock during the period of transition to the phase locked condition is not detected.
If the output of the FF 91 is "0" (at the inactive level) when the RST signal goes to active level, the outputs of the NAND gate 94 and the NAND gate 95 are both "1" (at active level), and the shift registers 92 and 93 are reset. Since the OVF outputs of both the shift registers 92 and 93 are at the "0" level, the output of the OR gate 96 is also at the "0" level. The LMCSGC 97 functions so as to output a "0" level signal REFEN and a "1" level signal FILTEN when "0" is input. Therefore, this clock generator functions as a PLL synthesizer, and the loop operates toward phase locked condition.
Once the loop is brought to the phase locked condition, the FF 91 is set, its output goes to the "1" level, and the outputs of the NAND gates 94 and 95 are determined by the state of the FF 91 and the state of the reference clock signal XTALCLK. Namely, at this time, the output of the NAND gate 94 is the inversion of the reference clock signal XTALCLK, and the output level of the NAND gate 95 which is the inversion of the output of the NAND gate 94 coincides with the level of the reference clock signal XTALCLK. Accordingly, the shift register 92 is released from the reset condition when the level of the reference clock signal XTALCLK goes to "1", the shifting operation of the shift register 92 is active, and conversely, the shift register 93 is released from the reset condition when the level of the reference clock signal XTALCLK goes to "0" the shifting operation of the shift register 93 is active.
The operation of the shift registers 92 and 93 is to count the continued duration of the "1" level of the signal given to the input terminal IN during the "0" level of the RST signal, using the clock given to the CLK input terminal.
An example of the configuration of the shift register is shown in FIG. 10. The shift register comprises D-Flip Flop latches (referred to as "DFFs" hereinafter) 101, 102, 103 and 104, and an AND gate 105. An input terminal CLK of the shift register 92 is connected to all input terminals CLKT of the DFFs 101, 102, 103 and 104, and an input signal RES is connected to all input terminals REST, an input terminal D of the DFF 101 is connected to the input terminal IN, its output Q is connected to the input terminal D of the DFF 102, the output Q of the DFF 102 is connected to the input terminal D of the DFF 103 and the output Q of the DFF 103 is connected to the input terminal D of the DFF 104. In addition, all of the outputs Q of the DFFs are connected to the inputs of the AND gate 105. During the period over which the signal inputted to the input terminal REST is at the "1" level, the output Q of each DFF goes to the "0" level, and the OVF signal which is the output of the AND gate 105 goes to the "0" level. As the input signal inputted to the input terminal REST goes to the "0" level, the data level of the input terminal D is shifted successively corresponding to the CLK input. The OVF signal which is the output of the AND gate 105 goes to the "1" level when all of the outputs Q of the DFFs are at the "1" level, which occurs when "1" level signals are kept input over four clock periods according to the clock of the input terminal CLKT.
Now, when the reference clock signal XTALCLK is given properly, the shift registers 92 and 93 described in the above are normally in a state where the frequencies of the reference clock signal XTALCLK and divided clock signal MCCLK are nearly equal. Therefore, the signal OVF is not generated from the shift registers 92 and 93, and they are mutually reset alternately corresponding to the changes in the reference clock signal XTALCLK level. Accordingly, the output of the OR gate 96 is always at the "0" level. Once the reference clock signal XTALCLK stays at the "1" level, the reset of the shift register 92 is released to perform the shifting operation to count the period of the reference clock signal XTALCLK level at the "1" corresponding to the divided clock signal MCCLK, generating an OVF of the shift register 92 to bring the output of the OR gate 96 to the "1" level. The shift register 93 is similarly the shift register 92. That is, the system described above possesses the function of detecting the loss of the reference clock. The LMCSGC 97 controls the output signals REFEN and FILTEN in response to the output "1" of the OR gate 96, and brings the signal REFEN to the "1" level and the signal FILTEN to the "0" level.
The operational timings of the limp control circuit 81 shown in FIG. 9 are given in FIG. 11. FIG. 11 shows the case when the reference clock signal XTALCLK is fixed to the "1" level. When the reference clock signal XTALCLK continues to remain at the "1" level, the output of the NAND gate 96 continues to stay at the "0" level, and the reset of the shift register 92 continues to be released. Moreover, since the level "1" of the reference clock signal XTALCLK continues to be given at this time to the IN input of the shift register 92, the shift register 92 sequentially shifts the data in response to the clock of the signal MCCLK and generates an OVF after four counts of the MCCLK signal, bringing the output of the OR gate 96 to the "1" level. In response to this, the LMCSGC 97 brings the signals REFEN and FILTEN to the "1" and the "0" levels, respectively.
When the reference clock signal XTALCLK continues to stay at the "0" level, the shift register 93 performs an operation similar to the shift register 92 as mentioned above.
As described in the above, the limp mode control circuit achieves the detection of the loss of the reference clock signal by two shift registers which measure the periods corresponding to the respective levels, the "0" and the "1" levels in this case, at the time of its detection.
Generally, the output signal of a crystal oscillator is used to a reference clock signal, it is not possible to determine the level at the time of loss of the reference clock signal to be fixed to the "0" level or the "1" level. Therefore, in the conventional device, the reference clock signal is observed directly two measuring means for measuring the respective periods of the "0" and "1" levels of the reference clock signal level at the time of loss of the reference clock signal, which leads to a drawback that a circuit area becomes large.